This invention relates generally to computer memory devices and more particularly to computer memory devices organized from charge coupled device shift registers. The subject invention further relates to a manner of controlling a memory device of three-phase charge coupled device shift registers.
Technology for constructing and operating three-phase charge-coupled device shift registers is now well-known. For example, such technology has been described by W. S. Boyle and G. E. Smith in an article entitled "Charge Coupled Semiconductor Devices" in the Bell System Technical Journal, April 1970, p. 587.
Large scale integrated charge-coupled device memories of high bit density (32K, 64K, or higher) have been generally suggested. In one type of organization, the shift register channels are laid out or "stacked" one after another with channel stoppers in between. Common gate electrode lines for clocking all of the charge-coupled device channels are then laid out perpendicular to the shift register channels. Straight and serpentine layouts of such stacked shift registers have been proposed, the latter being preferred in high-speed memories where closed loops are formed for refreshing. Either the straight or serpentine organizations result in the desired high bit density. However, since all the controlling phase voltages are applied to common gate electrode lines in the prior art, individual shift registers cannot be selectively operated. In addition, such prior art memory organizations have required closely spaced (typically 0.1 mil) electrodes, necessitating stringent photolithographic control.